Antenna module

ABSTRACT

An antenna module includes a connection member including at least one wiring layer and at least one insulating layer; an integrated circuit (IC) package disposed on a first surface of the connection member; and an antenna package including a plurality of antenna members and a plurality of feed vias, and disposed on a second surface of the connection member, wherein the IC package includes: an IC having an active surface electrically connected to at least one wiring layer and an inactive surface opposing the active surface, and generating the RF signal; a heat sink member disposed on the inactive surface of the IC; and an encapsulant encapsulating at least portions of the IC and the heat sink member.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims benefit of priority to Korean Patent Application No. 10-2017-0166856 filed on Dec. 6, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD 1. Field

The present disclosure relates to an antenna module.

BACKGROUND 2. Description of Related Art

Recently, millimeter wave (mmWave) communications, including 5th generation (5G) communications, have been actively researched, and research into the commercialization of an antenna module able to smoothly implement millimeter wave communications is being actively undertaken.

Conventionally, an antenna module providing a millimeter wave communications environment uses a structure in which an integrated circuit (IC) and an antenna are disposed on a board and are connected to each other by a coaxial cable in order to satisfy a high level of antennal performance (e.g., a transmission and reception rate, a gain, directivity, and the like) according to a high frequency.

However, such a structure may cause a shortage of antenna layout space, a restriction of the degree of freedom of an antenna shape, an increase in interference between the antenna and the IC, and an increase in the size/cost of the antenna module.

SUMMARY

An aspect of the present disclosure may provide an antenna module able to be easily miniaturized, while having a high level of antenna performance.

According to an aspect of the present disclosure, an antenna module may include a connection member including at least one wiring layer and at least one insulating layer; an integrated circuit (IC) package disposed on a first surface of the connection member; and an antenna package including a plurality of antenna members configured to transmit and receive a radio frequency (RF) signal, a plurality of feed vias in which one end of each thereof is electrically connected to each of the plurality of antenna members and the other end of each thereof is electrically connected to a corresponding wire of the at least one wiring layer, and a dielectric layer disposed to surround side surfaces of each of the plurality of feed vias and having a height greater than that of the at least one insulating layer, and disposed on a second surface of the connection member, wherein the IC package includes: an IC having an active surface electrically connected to the at least one wiring layer and an inactive surface opposing the active surface, and configured to generate the RF signal; a heat sink member disposed on the inactive surface of the IC; and an encapsulant encapsulating at least portions of the IC and the heat sink member.

According to another aspect of the present disclosure, an antenna module may include a connection member including at least one wiring layer and at least one insulating layer; an integrated circuit (IC) package disposed on a first surface of the connection member; and an antenna package including a plurality of antenna members configured to transmit and receive a radio frequency (RF) signal, a plurality of feed vias in which one end of each thereof is electrically connected to each of the plurality of antenna members and the other end of each thereof is electrically connected to a corresponding wire of the at least one wiring layer, and a dielectric layer disposed to surround side surfaces of each of the plurality of feed vias and having a height greater than that of the at least one insulating layer, and disposed on a second surface of the connection member, wherein the IC package includes: a first IC having a first active surface electrically connected to the at least one wiring layer and a first inactive surface opposing the first active surface and configured to generate the RF signal; a second IC having a second inactive surface facing the first inactive surface of the first IC and a second inactive surface opposing the second inactive surface and electrically connected to the at least one wiring layer, and configured to generate a base signal or power; a core via disposed on side surfaces of the first and second ICs and having one end electrically connected to the at least one wiring layer and the other end electrically connected to the second active surface; and an encapsulant encapsulating at least portions of the first and second ICs and the core via.

BRIEF DESCRIPTION OF DRAWINGS

The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view of an antenna module having a heat sink member according to an exemplary embodiment in the present disclosure;

FIG. 2 is a cross-sectional view of an antenna module having first and second ICs according to an exemplary embodiment in the present disclosure;

FIG. 3 is a view illustrating an example of an IC package included in an antenna module according to an exemplary embodiment in the present disclosure;

FIG. 4 is a view illustrating another example of an IC package included in an antenna module according to an exemplary embodiment in the present disclosure;

FIG. 5 is a cross-sectional view of an antenna module having first and second ICs according to an exemplary embodiment in the present disclosure;

FIG. 6 is a cross-sectional view of an antenna module having first and second ICs and a heat sink member according to an exemplary embodiment in the present disclosure;

FIG. 7 is a cross-sectional view of an antenna module having first and second ICs and a heat sink member according to an exemplary embodiment in the present disclosure;

FIGS. 8A through 8G are views illustrating a first process of manufacturing an IC package included in an antenna module according to an exemplary embodiment in the present disclosure;

FIGS. 9A through 9G are views illustrating a second process of manufacturing an IC package included in an antenna module according to an exemplary embodiment in the present disclosure;

FIG. 10 is a view illustrating an upper surface of an antenna module according to an exemplary embodiment in the present disclosure;

FIG. 11 is a view illustrating an upper surface of an antenna module according to an exemplary embodiment in the present disclosure;

FIGS. 12A through 12C are perspective views each illustrating an example of a cavity of an antenna package according to an exemplary embodiment in the present disclosure;

FIG. 13 is a perspective view illustrating an example of an antenna package according to an exemplary embodiment in the present disclosure;

FIG. 14 is a schematic block diagram illustrating an example of an electronic device system;

FIG. 15 is a schematic perspective view illustrating an example of an electronic device;

FIGS. 16A and 16B are a schematic cross-sectional view illustrating states of a fan-in semiconductor package before and after being packaged;

FIG. 17 is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package;

FIG. 18 is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is mounted on an interposer substrate and is finally mounted on a main board of an electronic device;

FIG. 19 is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is embedded in an interposer substrate and is finally mounted on a main board of an electronic device;

FIG. 20 is a schematic cross-sectional view illustrating a fan-out semiconductor package; and

FIG. 21 is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a main board of an electronic device.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view of an antenna module having a heat sink member according to an exemplary embodiment in the present disclosure.

Referring to FIG. 1, an antenna module according to an exemplary embodiment in the present disclosure may include an antenna package 100, a connection member 200, and an integrated circuit (IC) package.

Referring to FIG. 1, an antenna package 100 may include a plurality of antenna members 115 a, 115 b, 115 c, and 115 d configured to transmit or receive a radio frequency (RF) signal, a plurality of feed vias 120 a, 120 b, 120 c, and 120 d in which one end of each thereof is electrically connected to each of the plurality of antenna members 115 a, 115 b, 115 c, and 115 d and the other end of each of thereof is electrically connected to a corresponding wire of at least one wiring layer 210 a, and dielectric layers 140 a and 145 a having thicknesses greater than a thickness of at least one insulating layer 220 a of the connection member 200, and may be disposed on the connection member 200. Accordingly, the antenna module according to an exemplary embodiment in the present disclosure may have a radiation pattern in an upper direction to transmit and receive the RF signal.

Due to lengths of the feed vias 120 a, 120 b, 120 c, and 120 d and thicknesses of the dielectric layers 140 a and 145 a, a boundary condition for transmission and reception operation of the RF signal of the plurality of antenna members 115 a, 115 b, 115 c, and 115 d may be freely designed, and an unnecessary boundary condition (e.g., an interlayer interval, an interlayer implant, or the like) may be removed. Accordingly, since the feed vias 120 a, 120 b, 120 c, and 120 d and the dielectric layers 140 a and 145 a may provide boundary conditions (e.g., small manufacturing tolerance, a short electrical length, a smooth surface, a large margin space, a dielectric constant adjustment, and the like) advantageous to the transmission and reception operation of the RF signal of the plurality of antenna members 115 a, 115 b, 115 c, and 115 d, antenna performance of the plurality of antenna members 115 a, 115 b, 115 c, and 115 d may be improved.

The dielectric layers 140 a and 145 a may be formed of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, a resin in which the thermosetting resin or the thermoplastic resin is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, Ajinomoto Build up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like, and may be formed of a photo imagable dielectric (PID) resin depending on a design. For example, the dielectric layers 140 a and 145 a may be formed of a generic copper clad laminate (CCL) or a glass or ceramic based insulating material depending on required material characteristics. Depending on a design, the dielectric layers 140 a and 145 a may be formed of a material having a dielectric constant Dk higher than that of at least one insulating layer 220 a of the connection member 200.

Depending on a design, the antenna package 100 may further include a plurality of director members 110 a, 110 b, 110 c, and 110 d disposed on the plurality of antenna members 115 a, 115 b, 115 c, and 115 d and configured to transmit or receive a first RF signal together with the plurality of antenna members 115 a, 115 b, 115 c, and 115 d. The number of layers in which the plurality of director members 110 a, 110 b, 110 c, and 110 d are formed may be determined depending on a design condition of a gain and a height of the antenna module. Therefore, the number of layers is not limited to one.

Depending on a design, the antenna package 100 may include a plating member disposed to surround side surfaces of each of the feed vias 120 a, 120 b, 120 c, and 120 c and forming a plurality of cavities 130 a, 130 b, 130 c, and 130 d. The plurality of cavities 130 a, 130 b, 130 c, and 130 d may provide boundary conditions (e.g., a small manufacturing tolerance, a short electrical length, a smooth surface, a large margin space, an adjustment of a dielectric constant, and the like) advantageous in forming the radiation pattern of the plurality of antenna members 115 a, 115 b, 115 c, and 115 d, and may improve isolation between the plurality of antenna members 115 a, 115 b, 115 c, and 115 d.

Depending on a design, the antenna package 100 may further include an encapsulation member 150 a disposed on the plurality of antenna members 115 a, 115 b, 115 c, and 115 d. The encapsulation member 150 a may be changed to a solid state from a liquid state in a state in which it partially permeates down. Accordingly, structural stability of the antenna package 100 may be improved. In addition, the encapsulation member 150 a may be formed together with the plurality of director members 110 a, 110 b, 110 c, and 110 d in a process of forming the encapsulation member 150 a. The encapsulation member 150 a may be formed of a photo imageable encapsulant (PIE), Ajinomoto build-up film (ABF), epoxy molding compound (EMC), or the like, but is not limited thereto.

Depending on a design, the antenna package 100 may further include at least one second directional antenna member 170 a configured to extend in a direction toward the antenna package 100 at a corresponding position of at least one wiring layer 210 a and to transmit or receive the RF signal. That is, the antenna module according to an exemplary embodiment in the present disclosure may transmit and receive the RF signal in a side surface as well as an upper surface.

Meanwhile, the antenna member 115 a, 115 b, 115 c, and 115 d, the feed vias 120 a, 120 b, 120 c, and 120 d, and the plating member may be formed by a plating method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, subtractive, additive, semi-additive process (SAP), modified semi-additive process (MSAP), or the like, but is not limited thereto.

Referring to FIG. 1, the connection member 200 may include at least one wiring layer 210 a, at least one insulating layer 220 a, a wiring via 230 a, a connection pad 240 a, a passivation layer 250 a, and an electrical connection structure 290 a, and may have a structure similar to a copper redistribution layer.

For example, a portion and the remainder of each of at least one wiring layer 210 a, at least one insulating layer 220 a, and the wiring via 230 a included in the connection member 200 may be manufactured independently from each other and may be then connected to each other through the connection pad 240 a, the passivation layer 250 a, and the electrical connection structure 290 a. Depending on a design, since at least one wiring layer 210 a, at least one insulating layer 220, and wiring via 230 a may be integrally manufactured, the connection pad 240 a, the passivation layer 250 a, and the electrical connection structure 290 a may be omitted.

Referring to FIG. 1, the IC package may include an IC 300 a, an encapsulant 306 a, and a heat sink member 390 a.

The IC 300 a may have an active surface (e.g., an upper surface) electrically connected to at least one wiring layer 210 a and an inactive surface (e.g., a lower surface) opposing the active surface, and may transmit the RF signal to the antenna package 100 and receive the RF signal from the antenna package 100.

The active surface may be connected to an upper end wiring layer 310 a to secure a transfer path of the RF signal. Here, the upper end wiring layer 310 a and the insulating layer 280 a may be integrated with the connection member 200.

The IC 300 a may generate a large amount of heat in a process of generating and/or processing the RF signal. The heat may act as noise in the antenna package 100 or the connection member 200.

The encapsulant 306 a may encapsulate at least a portion of the IC 300 a and the heat sink member 390 a. The encapsulant 306 a may protect the IC 300 a and the heat sink member 390 a from external electrical/physical/chemical impact, and may be formed of a photo imageable encapsulant (PIE), Ajinomoto build-up film (ABF), epoxy molding compound (EMC), or the like, but is not limited thereto.

The heat sink member 390 a may be disposed on the inactive surface (e.g., the lower end) of the IC 300 a. The heat generated by the IC 300 a may be further concentrated on the heat sink member 390 a by the encapsulant 306 a and the heat sink member 390, and the heat sink member 390 a may discharge the transferred heat to the outside of the IC package.

Accordingly, a ratio of the heat transferred to the antenna package 100 or the connection member 200 among the heat generated by the IC 300 a may be reduced, and the antenna module according to an exemplary embodiment in the present disclosure may have more improved antenna performance.

In addition, since the heat sink member 390 a is disposed on the inactive surface of the IC 300 a, the heat sink member 390 a may be disposed to be adjacent to the IC 300 a. Accordingly, since a height of the antenna module according to an exemplary embodiment in the present disclosure may be shortened, the antenna module may be miniaturized.

Depending on a design, the IC package may further include a support member 355 a disposed on side surfaces of the IC 300 a and the heat sink member 390 a and having at least a portion encapsulated by the encapsulant 306 a. The support member 355 a may have a through-hole 355H in which the IC 300 a and the heat sink member 390 a are disposed, and thus may surround the side surfaces of the IC 300 a and the heat sink member 390 a. The support member 355 a may constrain the heat generated from the IC 300 a such that a significant portion of the heat generated from the IC 300 a may be transferred to the heat sink member 390 a.

Depending on a design, the support member 355 a may have a height higher than that of the IC 300 a, and the heat sink member 390 a may have a shape protruding in a direction viewing the IC 300 a. That is, the lower surface of the heat sink member 390 a may be below the lower surface of the support member 355 a. Accordingly, the heat generated from the IC 300 a may be more effectively guided to the heat sink member 390 a rather than to the support member 355 a, and the heat sink member 390 a may more rapidly discharge the transferred heat to the outside of the IC package.

Depending on a design, the IC package may further include a core plating member 365 a disposed on a side surface toward the IC 300 a and the heat sink member 390 a from the support member 355 a. The core plating member 365 a may absorb heat and noise generated from the IC 300 a, and may discharge the absorbed heat to the outside of the IC package.

Here, the heat sink member 390 a may be electrically connected to the core plating member 365 a at least through a lower end wiring layer 320 a disposed below a lower core wiring layer 359 a 2 of the support member 355 a. The heat sink member 390 a may include a heat sink member, for example, a metal block, and may be made of, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The heat sink member 390 a may be mounted to the IC 300 a by an adhesive layer 303 a. The heat sink member 390 a may further include a plating layer on the heat sink member by a process used to form the lower end wiring layer 320 a. Thus, the lower end wring layer 320 a and a lower portion of the heat sink member 390 a may be integrally formed and may be made of a conductive material used in the plating process. A thickness of the heat sink member 390 a may be greater than that of the lower end wiring layer 320 a. A lower surface of the heat sink member 390 and a lower surface of the lower end wiring layer 320 a may be on a same level while an upper surface of the heat sink member 390 may be on a level between upper and lower surfaces of the support member 355 a. Accordingly, the core plating member 365 a may more rapidly discharge the absorbed heat to the outside of the IC package. However, plating on the heat sink member may be omitted, and in this case, the heat sink member 390 may be spaced apart from the lower end wiring layer 320 a.

Meanwhile, the support member 355 a may include a core dielectric layer 356 a in contact with the upper end wiring layer 310 a, upper and lower core wiring layer 359 a 1 and 359 a 2 disposed on an upper surface and a lower surface of the core dielectric layer 356 a, and at least one core via 360 a penetrating through the core dielectric layer 356 a and electrically connecting the upper and lower core wiring layers 359 a 1 and 359 a 2 to each other. The upper core wiring layer 359 a 1 may be electrically connected to connection pads of the IC 300 a. At least portions of the lower end wiring layer 320 a may be electrically connected to the lower core wiring layer 359 a 2 and electrical connection structure 340 a such as a solder ball, a pin, and a land.

The core via 360 a may receive a base signal and/or power through the electrical connection structure 340 a, and may transmit the base signal and/or power to the active surface of the IC 300 a through the upper end wiring layer 310 a.

Here, the IC 300 a may generate an RF signal of a millimeter wave band (e.g., 28 GHz) based on the base signal and/or power, and may transmit the RF signal to the antenna package 100 through the active surface of the IC 300 a. For example, the IC 300 a may receive a base signal of a low frequency, and may perform a frequency conversion, amplification, a filtering phase control, and a power generation of the base signal.

Meanwhile, the IC package may further include passive components 351 a and 352 a electrically connected to a corresponding wire of the upper end wiring layer 310 a. The passive components 351 a and 352 a may be disposed in an accommodation space 307 a provided by the support member 355 a and may provide impedance to the IC 300 a. For example, the passive components 351 a and 352 a may include at least a portion of a multilayer ceramic capacitor (MLCC), an inductor, or a chip resistor.

In addition, the support member 355 a may further include core interior plating members 367 a and 368 a disposed to surround the passive components 351 a and 352 a in the accommodation space 307 a.

The passive components 351 a and 352 a may be isolated from the IC 300 a by the core plating member 365 a and/or the core interior plating members 367 a and 368 a. Accordingly, a negative influence (e.g., heat and noise) of the passive components 351 a and 352 a on the IC 300 a, the antenna package 100, and the connection member 200 may be reduced.

FIG. 2 is a cross-sectional view of an antenna module having first and second ICs according to an exemplary embodiment in the present disclosure.

Referring to FIG. 2, the IC package may include a first IC 301 a, a second IC 302 a, an encapsulant 305 a, a first heat sink member 391 a, and a second heat sink member 392 a.

The first IC 301 a may have a first active surface (e.g., an upper surface) electrically connected to at least one wiring layer 210 a and a first inactive surface (e.g., a lower surface) opposing the first active surface, and may transmit an RF signal to the antenna package 100 and receive the RF signal from the antenna package 100.

The second IC 302 a may have a second active surface (e.g., an upper surface) electrically connected to at least one wiring layer 210 a and a second inactive surface (e.g., a lower surface) opposing the second active surface, and may generate abase signal or power and transmit the base signal or power to the first IC 301 a.

Accordingly, since an electrical distance between the first IC 301 a and the second IC 302 a may be close, the second IC 302 a may more efficiently transmit the base signal or power to the first IC 301 a.

The encapsulant 305 a may encapsulate at least a portion of each of the first IC 301 a, the second IC 302 a, the first heat sink member 391 a, and the second heat sink member 392 a.

The first heat sink member 391 a may be disposed on the first inactive surface of the first IC 301 a.

The second heat sink member 392 a may be disposed on the second inactive surface of the second IC 302 a.

The second IC 302 a may generate a large amount of heat in a process of generating and/or processing the base signal or power. The heat may act as noise in the antenna package 100 or the connection member 200, and may also act as noise in the first IC 301 a.

That is, the second heat sink member 392 a may be disposed so that the heat generated from the second IC 302 a is more concentrated on the second heat sink member 392 a, and the second heat sink member 392 a may discharge the transferred heat to the outside of the IC package.

Accordingly, a ratio of the heat transferred to the antenna package 100, the connection member 200, or the first IC 301 a among the heat generated from the second IC 302 a may be reduced.

Depending on a design, the IC package may further include a support member 355 a having first and second IC cavities, in which the first IC 301 a and the second IC 302 a are respectively disposed. Accordingly, a negative influence (e.g., heat and noise) between the first IC 301 a and the second IC 302 a may be reduced.

In addition, the IC package may further include a core plating member 365 a disposed on side surfaces of the support member 355 a toward the first IC 301 a and the second IC 302 a. Accordingly, the negative influence between the first IC 301 a and the second IC 302 a may be further reduced, and the heat generated from the first IC 301 a and the second IC 302 a may be more efficiently discharged to the outside of the IC package.

Here, the core plating member 365 a may be electrically connected to at least one of the first heat sink member 391 a and the second heat sink member 392 a at least through a lower end wiring layer 320 a disposed below a lower core wiring layer 359 a 2 of the support member 355 a. Each of the first and second heat sink members 391 a and 392 a 2 may include a heat sink member, for example, a metal block, and may be made of, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first and second heat sink members 391 a and 392 a 2 may be mounted to the first and second ICs 301 a and 302 a by adhesive layers 303 a 1 and 303 a 2, respectively. Each heat sink members 391 a and 392 a 2 may further include a plating layer on the heat sink member by a process used to form the lower end wiring layer 320 a. Thus, the lower end wring layer 320 a and lower portions of the first and second heat sink members 391 a and 392 a may be integrally formed and may be made of a conductive material used in the plating process. A thickness of the first and second heat sink members 391 a and 392 a 2 may be greater than that of the lower end wiring layer 320 a. Lower surfaces of the first and second heat sink members 391 a and 392 a and a lower surface of the lower end wiring layer 320 a may be on a same level while upper surfaces of the first and second heat sink members 391 a and 392 a may be on a level between upper and lower surfaces of the support member 355 a. Accordingly, the core plating member 365 a may more rapidly discharge the absorbed heat to the outside of the IC package. However, plating on one or both heat sink members may be omitted, and in this case, one or both of the first and second heat sink members 391 a and 392 a may be spaced apart from the lower end wiring layer 320 a.

Other contents overlap those described above, and a detailed description thereof is thus omitted.

FIG. 3 is a view illustrating another example of an IC package included in an antenna module according to an exemplary embodiment in the present disclosure.

Referring to FIG. 3, the IC package may include at least portions of a first IC 401 a, a second IC 402 a, an adhesive member 403 a, an encapsulant 405 a, an upper end wiring layer 410 a, a lower end wiring layer 420 a, a passivation layer 430 a, a support member 455 a, a dielectric layer 456 a, a core wiring layer 459 a, and a core via 460 a.

The first IC 401 a may have a first active surface and a first inactive surface opposing the first active surface, and may generate an RF signal. Connection pads on the first active surfaces of the first IC 401 a may be electrically connected to a core wiring layer 459 a at least through an upper end wiring layer 410 a.

The second IC 402 a may generate a base signal or power and have a second inactive surface facing the first inactive surface of the first IC 401 a and a second active surface opposing the second inactive surface. Connection pads on the second active surfaces of the second IC 402 a may be electrically connected to a lower end wiring layer 420 a which may be connected to the upper end wiring layer 410 a at least through the core via 460 a.

Since the core via 460 a and the core wiring layer 459 a may be electrically connected to the upper end wiring layer 410 a or the lower end wiring layer 420 a, the base signal or power generated from the second IC 402 a may be transmitted to the first IC 401 a through the core via 460 a.

The IC package may further include a core plating member 465 a disposed on a side surface toward the first IC 401 a and the second IC 402 a. The core plating member 465 a may absorb heat and noise generated from the first IC 401 a and the second IC 402 a, and may discharge the absorbed heat to the outside of the IC package.

Since the first inactive surface of the first IC 401 a and the second inactive surface of the second IC 402 a are adjacent to each other, the IC package may be miniaturized or secure a layout margin of other components (e.g., a heat sink member and a passive component) to thereby improve antenna performance.

FIG. 4 is a view illustrating another example of an IC package included in an antenna module according to an exemplary embodiment in the present disclosure.

Referring to FIG. 4, connection pads of the first IC 401 may be electrically connected to the core via 460 a through a wire bonding. Other contents overlap those described above with reference to FIG. 3, and a detailed description thereof is thus omitted.

FIG. 5 is a cross-sectional view of an antenna module having first and second ICs according to an exemplary embodiment in the present disclosure.

Referring to FIG. 5, the IC package may include at least portions of a first IC 301 b, a second IC 302 b, an adhesive member 303 b, an encapsulant 305 b, an upper end wiring layer 310 b, a lower end wiring layer 320 b, a passivation layer 330 b, and a support member, and the support member may include at least portions of a dielectric layer 356 b, a core wiring layer 359 b, a core via 360 b, and a core plating member 365 b.

The IC package may have a structure similar to the IC package illustrated in FIG. 3 and may be disposed on a lower surface of the connection member 200.

Meanwhile, the first IC 301 b may have a size different from a size of the second IC 302 b and may be bonded to an inactive surface of the second IC 302 b through the adhesive member 303 b. The encapsulant 305 b may cover the inactive surface of the first IC 301 b exposed from the second IC 302 b.

In addition, a heat sink member 390 b may extend to cover a portions of the inactive surface of the first IC 301 b and be connected to the connection pad 240 a.

Other elements in FIG. 5, not described here and labeled with “xxxY” in which “xxx” is a number and “Y” is a letter, correspond to the above-described elements labeled with “xxxZ” in which “xxx” is a number and “Z” is letter. A detailed description of contents overlapping those described above is thus omitted.

FIG. 6 is a cross-sectional view of an antenna module having first and second ICs and a heat sink member according to an exemplary embodiment in the present disclosure.

Referring to FIG. 6, the IC package may further include a first heat sink member 391 b and a second heat sink member 392 b disposed to occupy at least a portion of a space generated according to a difference between the size of the first IC 301 b and the size of the second IC 302 b. In this case, an encapsulant 305 b may not completely occupy the space generated according to the difference between the size of the first IC 301 b and the size of the second IC 302 b.

Accordingly, heat generated from each of the first IC 301 b and the second IC 302 b may be efficiently concentrated on the first heat sink member 391 b and the second heat sink member 392 b, and the first heat sink member 391 b and the second heat sink member 392 b may rapidly discharge the transferred heat.

In addition, since the first heat sink member 391 b and the second heat sink member 392 b do not substantially increase a height of the IC package, the antenna module according to an exemplary embodiment in the present disclosure may improve antenna performance without substantially increasing a size thereof.

Other elements in FIG. 6, not described here and labeled with “xxxY” in which “xxx” is a number and “Y” is a letter, correspond to the above-described elements labeled with “xxxZ” in which “xxx” is a number and “Z” is a letter. A detailed description of contents overlapping those described above is thus omitted.

FIG. 7 is a cross-sectional view of an antenna module having first and second ICs and a heat sink member according to an exemplary embodiment in the present disclosure.

Referring to FIG. 7, the IC package may include a heat sink member 390 c disposed between the inactive surface of the first IC 301 c and the inactive surface of the second IC 302 c.

For example, the heat sink member 390 c may have a structure in which it is inserted between the inactive surface of the first IC 301 c and the inactive surface of the second IC 302 c through a region which is not covered by the lower end wiring layer 320 c and the electrical connection structure 340 c.

Accordingly, heat generated from each of the first IC 301 c and the second IC 302 c may be efficiently concentrated on the heat sink member 390 c, and the heat sink member 390 c may rapidly discharge the transferred heat.

In addition, since the heat sink member 390 c does not substantially increase the height of the IC package, the antenna module according to an exemplary embodiment in the present disclosure may improve antenna performance without substantially increasing the size thereof.

Other elements in FIG. 7, not described here and labeled with “xxxY” in which “xxx” is a number and “Y” is a letter, correspond to the above-described elements “xxxZ” in which “xxx” is a number and “Z” is a letter. A detailed description of contents overlapping those described above is thus omitted.

FIGS. 8A through 8G are views illustrating a first process of manufacturing an IC package included in an antenna module according to an exemplary embodiment in the present disclosure.

Referring to FIG. 8A, a support member 355 h may be provided on a film 380 h while having at least one hole, and a core via 360 h may be formed in at least one hole of the support member 355 h.

Referring to FIG. 8B, the core dielectric layer 356 h may be formed on an upper surface and a lower surface of the support member 355 h, and a heat sink member 390 h such as a metal block which is releasable/removable from the support member 355 h may be formed in the support member 355 h.

Referring to FIG. 8C, a region in which at least one IC 300 h is to be disposed in the support member 355 h may be removed, and a core plating member 365 h may be formed on a side surface of the region.

Referring to FIG. 8D, at least one IC 300 h may be disposed in the region and at least one IC 300 h may be encapsulated by the encapsulant.

Referring to FIG. 8E, a film 380 h may be removed and an insulating layer 280 h may be formed on a lower surface of the IC 300 h.

Referring to FIG. 8F, a wiring layer 310 h may be formed on a lower surface of the insulating layer 280 h and may be electrically connected to an active surface of the IC 300 h.

Referring to FIG. 8G, a connection pad 240 h and a passivation layer 250 h may be disposed on the wiring layer 310 h, and at least a portion of the heat sink member 390 h may be removed. The passive component and/or the second IC may be disposed in the region in which the heat sink member 390 h is positioned.

FIGS. 9A through 9G are views illustrating a second process of manufacturing an IC package included in an antenna module according to an exemplary embodiment in the present disclosure.

Referring to FIG. 9A, a support member 355 i may be provided on a film 380 i while having at least one hole and an accommodation space 306 i, a core via 360 i may be formed in at least one hole of the support member 355 i, and a passive component 350 i may be disposed in the accommodation space 306 i.

Referring to FIG. 9B, a core dielectric layer 356 i may be formed on an upper surface and a lower surface of the support member 355 i.

Referring to FIG. 9C, a region in which at least one IC 300 i and a heat sink member 390 i are to be disposed in the support member 355 i may be removed, a core plating member 365 i may be formed on a side surface of the region, and at least one IC 300 i and the heat sink member 390 i may be disposed in the region.

Referring to FIG. 9D, at least one IC 300 i and the heat sink member 390 i may be encapsulated by an encapsulant 305 i. The IC package may be then rotated by 180°.

Referring to FIG. 9E, the film 380 h may be removed and an insulating layer 280 i may be formed on an upper surface of the IC 300 i.

Referring to FIG. 9F, a wiring layer 310 i may be formed on an upper surface of the insulating layer 280 i and may be electrically connected to an active surface of the IC 300 i.

Referring to FIG. 9G, a connection pad 240 i and a passivation layer 250 i may be disposed on the wiring layer 310 i.

Meanwhile, the plating layers/members, the core vias, the core plating members, the heat sink members, and wiring layers may be formed of a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, and may be formed by a plating method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, subtractive, additive, semi-additive process (SAP), modified semi-additive process (MSAP), or the like, but is not limited thereto.

FIG. 10 is a view illustrating an upper surface of an antenna module according to an exemplary embodiment in the present disclosure.

Referring to FIG. 10, each of a plurality of director members 110 a, 110 b, 110 c, 110 d, 110 e, 110 f, 110 g, 110 h, 110 i, 110 j, 110 k, 110 l, 110 m, 110 n, 110 o, and 110 p may have a form of a patch antenna, and may be surrounded by a corresponding plating member of a plurality of plating members 160 a, 160 b, 160 c, 160 d, 160 e, 160 f, 160 g, 160 h, 160 i, 160 j, 160 k, 160 l, 160 m, 160 n, 160 o, and 160 p. If the antenna module does not include the plurality of director members, the plurality of director members 110 a, 110 b, 110 c, 110 d, 110 e, 110 f, 110 g, 110 h, 110 i, 110 j, 110 k, 110 l, 110 m, 110 n, 110 o, and 110 p may be replaced with a plurality of antenna members.

FIG. 11 is a view illustrating an upper surface of an antenna module according to an exemplary embodiment in the present disclosure.

Referring to FIG. 11, each of a plurality of director members 110-1, 110-2, 110-3, 110-4, 110-5, 110-6, 110-7, 110-8, and 110-9 may be surrounded by at least one of corresponding plating members 160-1, 160-2, 160-3, 160-4, 160-5, 160-6, 160-7, 160-8, and 160-9, and a plurality of shielding members 190-1, 190-2, 190-3, 190-4, 190-5, 190-6, 190-7, 190-8, and 190-9. If the antenna module does not include the plurality of director members, the plurality of director members 110-1, 110-2, 110-3, 110-4, 110-5, 110-6, 110-7, 110-8, and 110-9 may be replaced with a plurality of antenna members.

Meanwhile, the number, layout, and shape of the plurality of director members or the plurality of antenna members illustrated in FIGS. 10 and 11 are not particularly limited. For example, the shape of the plurality of director members illustrated in FIG. 10 may be circular shape, and the number of the plurality of antenna members illustrated in FIG. 11 may be four.

FIGS. 12A through 12C are perspective views each illustrating an example of a cavity of an antenna package according to an exemplary embodiment in the present disclosure.

Referring to FIG. 12A, a cavity may include at least portions of a director member 110 e, an antenna member 115 e, a feed via, an electrical connection structure, a dielectric layer 130 e, and a plating member 160 e. Here, the plating member 160 e may be disposed to surround side surfaces of the cavity. That is, a lower surface of the cavity may be covered by a ground pattern disposed on an upper surface of the connection member.

Referring to FIG. 12B, the cavity may include at least portions of a director member 110 f, an antenna member 115 f, a feed via 120 f, an electrical connection structure 125 f, a dielectric layer 130 f, and a plating member 160 f. Here, the plating member 160 f may be disposed to cover a portion of the lower surface of the cavity. That is, the side surfaces of the cavity may be surrounded by the plating member disposed on side surfaces of an insulating member on the connection member. Accordingly, isolation between the connection member and the IC of the antenna package may be improved.

Referring to FIG. 12C, the cavity may include at least portions of an antenna member 110 g, a feed via 120 g, an electrical connection structure 125 g, and a dielectric layer 130 g. That is, the side surfaces of the cavity may be surrounded by the plating member disposed on the side surfaces of the insulating member on the connection member, and the lower surface of the cavity may be covered by the ground pattern disposed on the upper surface of the connection member.

Meanwhile, the electrical connection structures 125 f and 125 g may be connected to a corresponding wire of at least one wiring layer 210 of the connection member when the antenna package and the connection member are coupled to each other. For example, the electrical connection structures 125 f and 125 g may be implemented in electrodes, pins, solder balls, lands, and the like.

FIG. 13 is a perspective view illustrating an example of an antenna package according to an exemplary embodiment in the present disclosure.

Referring to FIG. 13, an antenna package may include a plurality of director members 110 d, a cavity 130 d, a dielectric layer 140 d, a plating member 160 d, a plurality of directional antennal member 170 c and 170 d, and a plurality of dipole antennas 175 c and 175 d.

The plurality of director members 110 d may transmit and receive an RF signal in a z axis direction together with corresponding antenna members.

The plurality of second directional antenna members 170 c and 170 d may be disposed to be adjacent to an edge of the antenna package and to be stood up in the z axis direction, and one of the plurality of directional antennas 170 c and 170 d may transmit and receive a second RF signal in an x axis direction and the other thereof may transmit and receive the second RF signal in a y axis direction.

The plurality of dipole antennas 175 c and 175 d may be disposed between the dielectric layer 140 d and an encapsulation member to be adjacent to the edge of the antenna package, and one of the plurality of dipole antennas 175 c and 175 d may transmit and receive a third RF signal in the x axis direction and the other thereof may transmit and receive the third RF signal in the y axis direction. Depending on a design, at least a portion of the plurality of dipole antennas 175 c and 175 d may be replaced with a monopole antenna.

Meanwhile, the IC package disclosed herein may be implemented according to a fan-out semiconductor package to be described below. To facilitate understanding of the fan-out semiconductor package, a description will be made with reference to FIGS. 14 through 21.

FIG. 14 is a schematic block diagram illustrating an example of an electronic device system.

Referring to FIG. 14, an electronic device 1000 may accommodate a mainboard 1010 therein. The mainboard 1010 may include chip related components 1020, network related components 1030, other components 1040, and the like, physically or electrically connected thereto. These components may be connected to others to be described below to form various signal lines 1090.

The chip related components 1020 may include a memory chip such as a volatile memory (for example, a dynamic random access memory (DRAM)), a non-volatile memory (for example, a read only memory (ROM)), a flash memory, or the like; an application processor chip such as a central processor (for example, a central processing unit (CPU)), a graphics processor (for example, a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like; and a logic chip such as an analog-to-digital (ADC) converter, an application-specific integrated circuit (ASIC), or the like. However, the chip related components 1020 are not limited thereto, but may also include other types of chip related components. In addition, the chip related components 1020 may be combined with each other.

The network related components 1030 may include protocols such as wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, or the like), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, or the like), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access+ (HSPA+), high speed downlink packet access+ (HSDPA+), highspeed uplink packet access+ (HSUPA+), enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, and 5G protocols, and any other wireless and wired protocols designated after the abovementioned protocols. However, the network related components 1030 are not limited thereto, but may also include a variety of other wireless or wired standards or protocols. In addition, the network related components 1030 may be combined with each other, together with the chip related components 1020 described above.

Other components 1040 may include a high frequency inductor, a ferrite inductor, a power inductor, ferrite beads, a low temperature co-fired ceramic (LTCC), an electromagnetic interference (EMI) filter, a multilayer ceramic capacitor (MLCC), or the like. However, other components 1040 are not limited thereto, but may also include passive components used for various other purposes, or the like. In addition, other components 1040 may be combined with each other, together with the chip related components 1020 or the network related components 1030 described above.

Depending on a type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically or electrically connected to the mainboard 1010. These other components may include, for example, a camera module 1050, an antenna 1060, a display device 1070, a battery 1080, an audio codec (not illustrated), a video codec (not illustrated), a power amplifier (not illustrated), a compass (not illustrated), an accelerometer (not illustrated), a gyroscope (not illustrated), a speaker (not illustrated), a mass storage unit (for example, a hard disk drive) (not illustrated), a compact disk (CD) drive (not illustrated), a digital versatile disk (DVD) drive (not illustrated), or the like. However, these other components are not limited thereto, but may also include other components used for various purposes depending on a type of electronic device 1000, or the like.

The electronic device 1000 may be a smartphone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game machine, a smartwatch, an automotive component, or the like. However, the electronic device 1000 is not limited thereto, but may be any other electronic device processing data.

FIG. 15 is a schematic perspective view illustrating an example of an electronic device.

Referring to FIG. 15, an electronic device may be, for example, a smartphone 1100. In the smartphone 1100, a radio frequency integrated circuit (RFIC) may be used in a semiconductor package form, and an antenna may be used in a substrate or module form. The RFIC and the antenna may be electrically connected to each other in the smartphone 1100, and radiation R of antenna signals in various directions may be thus possible. A semiconductor package including the RFIC and a substrate or a module including the antenna may be used in various forms in an electronic device such as the smartphone, or the like.

Generally, numerous fine electrical circuits are integrated in a semiconductor chip. However, the semiconductor chip may not serve as a finished semiconductor product in itself, and may be damaged due to external physical or chemical impacts. Therefore, the semiconductor chip itself may not be used, but may be packaged and used in an electronic device, or the like, in a packaged state.

Here, semiconductor packaging is required due to the existence of a difference in a circuit width between the semiconductor chip and a mainboard of the electronic device in terms of electrical connections. In detail, a size of connection pads of the semiconductor chip and an interval between the connection pads of the semiconductor chip are very fine, but a size of component mounting pads of the mainboard used in the electronic device and an interval between the component mounting pads of the mainboard are significantly larger than those of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the mainboard, and packaging technology for buffering a difference in a circuit width between the semiconductor chip and the mainboard is required.

A semiconductor package manufactured by the packaging technology may be classified as a fan-in semiconductor package or a fan-out semiconductor package depending on a structure and a purpose thereof.

The fan-in semiconductor package and the fan-out semiconductor package will hereinafter be described in more detail with reference to the drawings.

FIGS. 16A and 16B are schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged.

FIG. 17 is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package.

Referring to FIGS. 16A, 16B and 17, a semiconductor chip 2220 may be, for example, an integrated circuit (IC) in a bare state, including a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, connection pads 2222 formed on one surface of the body 2221 and including a conductive material such as aluminum (Al), or the like, and a passivation layer 2223 such as an oxide film, a nitride film, or the like, formed on one surface of the body 2221 and covering at least portions of the connection pads 2222. In this case, since the connection pads 2222 are significantly small, it is difficult to mount the integrated circuit (IC) on an intermediate level printed circuit board (PCB) as well as on the mainboard of the electronic device, or the like.

Therefore, a connection member 2240 may be formed depending on a size of the semiconductor chip 2220 on the semiconductor chip 2220 in order to redistribute the connection pads 2222. The connection member 2240 may be formed by forming an insulating layer 2241 on the semiconductor chip 2220 using an insulating material such as photoimagable dielectric (PID) resin, forming via holes 2243 h opening the connection pads 2222, and then forming wiring patterns 2242 and vias 2243. Then, a passivation layer 2250 protecting the connection member 2240 may be formed, an opening 2251 may be formed, and an underbump metal layer 2260, or the like, may be formed. That is, a fan-in semiconductor package 2200 including, for example, the semiconductor chip 2220, the connection member 2240, the passivation layer 2250, and the under-bump metal layer 2260 may be manufactured through a series of processes.

As described above, the fan-in semiconductor package may have a package form in which all of the connection pads, for example, input/output (I/O) terminals, of the semiconductor chip, are disposed inside the semiconductor chip, and may have excellent electrical characteristics and be produced at a low cost. Therefore, many elements mounted in smartphones have been manufactured in a fan-in semiconductor package form. In detail, many elements mounted in smartphones have been developed to implement a rapid signal transfer while having a compact size.

However, since all I/O terminals need to be disposed inside the semiconductor chip in the fan-in semiconductor package, the fan-in semiconductor package has a large spatial limitation. Therefore, it is difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a compact size. In addition, due to the disadvantage described above, the fan-in semiconductor package may not be directly mounted and used on the mainboard of the electronic device. The reason is that even in a case that a size of the I/O terminals of the semiconductor chip and an interval between the I/O terminals of the semiconductor chip are increased by a redistribution process, the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in semiconductor package on the mainboard of the electronic device.

FIG. 18 is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is mounted on an interposer substrate and is ultimately mounted on a mainboard of an electronic device.

FIG. 19 is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is embedded in an interposer substrate and is ultimately mounted on a mainboard of an electronic device.

Referring to FIGS. 18 and 19, in a fan-in semiconductor package 2200, connection pads 2222, that is, I/O terminals, of a semiconductor chip 2220 may be redistributed through an interposer substrate 2301, and the fan-in semiconductor package 2200 may be ultimately mounted on a mainboard 2500 of an electronic device in a state in which it is mounted on the interposer substrate 2301. In this case, solder balls 2270, and the like, may be fixed by an underfill resin 2280, or the like, and an outer side of the semiconductor chip 2220 may be covered with a molding material 2290, or the like. Alternatively, a fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, connection pads 2222, that is, I/O terminals, of the semiconductor chip 2220 may be redistributed by the interposer substrate 2302 in a state in which the fan-in semiconductor package 2200 is embedded in the interposer substrate 2302, and the fan-in semiconductor package 2200 may be ultimately mounted on a mainboard 2500 of an electronic device.

As described above, it may be difficult to directly mount and use the fan-in semiconductor package on the mainboard of the electronic device. Therefore, the fan-in semiconductor package may be mounted on the separate interposer substrate and be then mounted on the mainboard of the electronic device through a packaging process or may be mounted and used on the mainboard of the electronic device in a state in which it is embedded in the interposer substrate.

FIG. 20 is a schematic cross-sectional view illustrating a fan-out semiconductor package.

Referring to FIG. 20, in a fan-out semiconductor package 2100, for example, an outer side of a semiconductor chip 2120 may be protected by an encapsulant 2130, and connection pads 2122 of the semiconductor chip 2120 may be redistributed outwardly of the semiconductor chip 2120 by a connection member 2140. In this case, a passivation layer 2150 may be further formed on the connection member 2140, and an underbump metal layer 2160 may be further formed in openings of the passivation layer 2150. Solder balls 2170 may be further formed on the underbump metal layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, the connection pads 2122, a passivation layer (not illustrated), and the like. The connection member 2140 may include an insulating layer 2141, redistribution layers 2142 formed on the insulating layer 2141, and vias 2143 electrically connecting the connection pads 2122 and the redistribution layers 2142 to each other.

As described above, the fan-out semiconductor package may have a form in which I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip need to be disposed inside the semiconductor chip. Therefore, when a size of the semiconductor chip is decreased, a size and a pitch of balls need to be decreased, such that a standardized ball layout may not be used in the fan-in semiconductor package. On the other hand, the fan-out semiconductor package has the form in which the I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip as described above. Therefore, even in a case that a size of the semiconductor chip is decreased, a standardized ball layout may be used in the fan-out semiconductor package as it is, such that the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using a separate interposer substrate, as described below.

FIG. 21 is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a mainboard of an electronic device.

Referring to FIG. 21, a fan-out semiconductor package 2100 may be mounted on a mainboard 2500 of an electronic device through solder balls 2170, or the like. That is, as described above, the fan-out semiconductor package 2100 includes the connection member 2140 formed on the semiconductor chip 2120 and capable of redistributing the connection pads 2122 to a fan-out region that is outside of a size of the semiconductor chip 2120, such that the standardized ball layout may be used in the fan-out semiconductor package 2100 as it is. As a result, the fan-out semiconductor package 2100 may be mounted on the mainboard 2500 of the electronic device without using a separate interposer substrate, or the like.

As described above, since the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using the separate interposer substrate, the fan-out semiconductor package may be implemented at a thickness lower than that of the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package may be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal characteristics and electrical characteristics, such that it is particularly appropriate for a mobile product. Therefore, the fan-out semiconductor package may be implemented in a form more compact than that of a general package-on-package (POP) type using a printed circuit board (PCB), and may solve a problem due to occurrence of a warpage phenomenon.

Meanwhile, the fan-out semiconductor package refers to package technology for mounting the semiconductor chip on the mainboard of the electronic device, or the like, as described above, and protecting the semiconductor chip from external impacts, and is a concept different from that of a printed circuit board (PCB) such as an interposer substrate, or the like, having a scale, a purpose, and the like, different from those of the fan-out semiconductor package, and having the fan-in semiconductor package embedded therein.

As set forth above, according to the exemplary embodiments in the present disclosure, the antenna module may be easily miniaturized, while having the high level of antenna performance.

The antenna module according to the exemplary embodiment in the present disclosure may efficiently discharge the heat by concentrating the heat generated from the IC on the heat sink member.

The antenna module according to the exemplary embodiment in the present disclosure may reduce a negative influence (e.g., heat, noise) between the plurality of ICs while using the plurality of ICs and may be miniaturized.

The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with one another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.

While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims. 

What is claimed is:
 1. An antenna module comprising: a connection member including at least one wiring layer and at least one insulating layer; an integrated circuit (IC) package disposed on a first surface of the connection member; and an antenna package including a plurality of antenna members configured to transmit and receive a radio frequency (RF) signal, a plurality of feed vias in which one end of each thereof is electrically connected to each of the plurality of antenna members and the other end of each of thereof is electrically connected to a corresponding wire of the at least one wiring layer of the connection member, and a dielectric layer disposed to surround side surfaces of each of the plurality of feed vias and having a height greater than that of the at least one insulating layer of the connection member, and disposed on a second surface of the connection member, wherein the IC package includes: a first IC having a first active surface electrically connected to the at least one wiring layer and a first inactive surface opposing the first active surface, and configured to generate the RF signal; a first heat sink member disposed on the first inactive surface of the first IC; and an encapsulant encapsulating at least portions of the first IC and the first heat sink member.
 2. The antenna module of claim 1, wherein the IC package further includes: a support member having a through-hole in which the first IC and the first heat sink member are disposed and having at least a portion encapsulated by the encapsulant; and a core plating member disposed on a side surface of the support member toward the first IC and the first heat sink member, and the first heat sink member is electrically connected to the core plating member.
 3. The antenna module of claim 2, wherein the support member includes a core insulating layer, a core via penetrating through the core insulating layer and electrically connected to a corresponding wire of the at least one wiring layer, and a core wiring layer disposed on a first surface or a second surface of the core insulating layer and electrically connected to the core via.
 4. The antenna module of claim 2, wherein the IC package further includes a passive component electrically connected to a corresponding wire of the at least one wiring layer, and the supporting member provides an accommodation space accommodating the passive component.
 5. The antenna module of claim 4, wherein the support member further includes a core interior plating member disposed to surround the passive component in the accommodation space.
 6. The antenna module of claim 2, wherein the support member has a height greater than that of the first IC, and the first heat sink member protrudes from a level of a lower surface of the support member.
 7. The antenna module of claim 1, wherein the IC package further includes: a core via having one end electrically connected to a corresponding wire of the at least one wiring layer, and other end electrically connected to an electrical connection structure.
 8. The antenna module of claim 7, wherein the core via receives a base signal or power through the electrical connection structure and transmits the base signal or power to the active surface of the first IC, and the first IC generates the RF signal of a millimeter wave (mmWave) band based on the base signal or power and transmits the RF signal to the plurality of antenna members through the active surface of the first IC.
 9. The antenna module of claim 1, wherein the IC package further includes: a second IC having a second active surface electrically connected to the at least one wiring layer and a second inactive surface opposing the second active surface, and configured to generate a base signal or power and transmit the base signal or power to the first IC; and a second heat sink member disposed on the second inactive surface of the second IC.
 10. The antenna module of claim 9, wherein the IC package further includes: a support member having first and second through-holes in which the first IC and the second IC are respectively disposed; and core plating members disposed on side surfaces of the support member toward the first IC and the second IC, and at least one of the first heat sink member and the second heat sink member is electrically connected to the core plating member.
 11. An antenna module comprising: a connection member including at least one wiring layer and at least one insulating layer; an integrated circuit (IC) package disposed on a first surface of the connection member; and an antenna package including a plurality of antenna members configured to transmit and receive a radio frequency (RF) signal, a plurality of feed vias in which one end of each thereof is electrically connected to each of the plurality of antenna members and the other end of each of thereof is electrically connected to a corresponding wire of the at least one wiring layer of the connection member, and a dielectric layer disposed to surround side surfaces of each of the plurality of feed vias and having a height greater than that of the at least one insulating layer of the connection member, and disposed on a second surface of the connection member, wherein the IC package includes: a first IC having a first active surface electrically connected to the at least one wiring layer and a first inactive surface opposing the first active surface and configured to generate the RF signal; a second IC having a second inactive surface facing the first inactive surface of the first IC and a second inactive surface opposing the second inactive surface and electrically connected to the at least one wiring layer, and configured to generate a base signal or power; a core via disposed on side surfaces of the first and second ICs and having one end electrically connected to the at least one wiring layer and the other end electrically connected to the second active surface; and an encapsulant encapsulating at least portions of the first and second ICs and the core via.
 12. The antenna module of claim 11, wherein the IC package further includes an adhesive member bonding between the first inactive surface of the first IC and the second inactive surface of the second IC.
 13. The antenna module of claim 11, wherein the first IC has a size different from that of the second IC, and the IC package further includes a heat sink member occupying at least a portion of a space generated according to a difference in the size of the first IC and the size of the second IC.
 14. The antenna module of claim 11, wherein the IC package further includes a heat sink member disposed between the first inactive surface of the first IC and the second inactive surface of the second IC.
 15. The antenna module of claim 14, wherein the IC package further includes: a support member including the core via having a through-hole in which the first and second ICs are disposed; and a core plating member disposed on a side surface toward the first and second ICs from the support member, and the heat sink member is electrically connected to the core plating member.
 16. The antenna module of claim 15, wherein the support member includes: a core via electrically connected to a corresponding wire of the at least one wiring layer, a core insulating layer surrounding side surfaces of the core via, and a core wiring layer disposed on a first surface or a second surface of the core insulting layer and electrically connected to the core via, and the core wiring layer is electrically connected to at least one of the first and second active surfaces. 